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FEATURES 2-Wire Serial Interface 2.7 V to 5.5 V Single Supply 2.5 On Resistance 0.75 On-Resistance Flatness 100 pA Leakage Currents Single 8-to-1 Matrix Switch ADG728 Dual 4-to-1 Matrix Switch ADG729 Power-On Reset Small 16-Lead TSSOP Package APPLICATIONS Data Acquisition Systems Communication Systems Relay Replacement Audio and Video Switching Automatic Test Equipment
CMOS, Low-Voltage, 2-Wire Serially-Controlled, Matrix Switches ADG728/ADG729
FUNCTIONAL BLOCK DIAGRAMS
ADG728
S1 S1A DA S4A D S1B DB S8 INPUT SHIFT REGISTER RESET SDA SCL A0 A1 SDA SCL A0 A1 S4B INPUT SHIFT REGISTER
ADG729
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG728 and ADG729 are CMOS analog matrix switches with a serially controlled 2-wire interface. The ADG728 is an 8-channel matrix switch, while the ADG729 is a dual 4-channel matrix switch. On resistance is closely matched between switches and very flat over the full signal range. These parts can operate equally well as either multiplexers, demultiplexers or switch arrays and the input signal range extends to the supplies. The ADG728 and ADG729 utilize a 2-wire serial interface that is compatible with the I2CTM interface standard. Both have two external address pins (A0 and A1). This allows the 2 LSBs of the 7-bit slave address to be set by the user. Four of each of the devices can be connected to the one bus. The ADG728 also has a RESET pin that should be tied high if not in use. Each channel is controlled by one bit of an 8-bit word. This means that these devices may be used in a number of different configurations; all, any, or none of the channels may be on at any one time. On power-up of the device, all switches will be in the OFF condition and the internal shift register will contain all zeros. All channels exhibit break-before-make switching action preventing momentary shorting when switching channels. The ADG728 and ADG729 are available in 16-lead TSSOP packages.
1. 2-Wire Serial Interface. 2. Single Supply Operation. The ADG728 and ADG729 are fully specified and guaranteed with 3 V and 5 V supply rails. 3. Low On Resistance 2.5 typical. 4. Any configuration of switches may be on at any one time. 5. Guaranteed Break-Before-Make Switching Action. 6. Small 16-Lead TSSOP Package.
I2C is a trademark of Philips Corporation.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
ADG728/ADG729-SPECIFICATIONS1 (V
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) LOGIC INPUTS (A0, A1)2 Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Input Capacitance LOGIC INPUTS (SCL, SDA)2 Input High Voltage, VINH Input Low Voltage, VINL IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance LOGIC OUTPUT (SDA)2 VOL, Output Low Voltage DYNAMIC CHARACTERISTICS2 tON tOFF Break-Before-Make Time Delay, tD Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth ADG728 ADG729 CS (OFF) CD (OFF) ADG728 ADG729 CD, CS (ON) ADG728 ADG729 POWER REQUIREMENTS IDD
NOTES
Temperature range is as follows: B Version: -40C to +85C. Guaranteed by design, not subject to production test. Specifications subject to change without notice.
2 1
DD
=5V
10%, GND = 0 V, unless otherwise noted.)
B Version -40 C 25 C to +85 C 0 V to VDD 2.5 4.5 0.75 1.2 0.01 0.1 0.01 0.1 0.01 0.1 5 0.4 0.8
Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ V min V max V min V max A typ A max V min pF typ V max V max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ dB typ MHz typ MHz typ pF typ pF typ pF typ pF typ pF typ A typ A max
Test Conditions/Comments
VS = 0 V to VDD, IS = 10 mA; Test Circuit 1 VS = 0 V to VDD, IS = 10 mA VS = 0 V to VDD, IS = 10 mA VDD = 5.5 V VD = 4.5 V/1 V, VS = 1 V/4.5 V, Test Circuit 2 VD = 4.5 V/1 V, VD = 1 V/4.5 V, Test Circuit 3 VD = VS = 4.5 V/1 V, Test Circuit 4
0.3 1 1 2.4 0.8
0.005 6
0.1
0.7 VDD VDD + 0.3 -0.3 0.3 VDD 0.005 0.05 VDD 6 0.4 0.6 95 140 85 130 8 3 -55 -75 -55 -75 65 100 13 85 42 96 48 10 20 1 1.0
VIN = 0 V to VDD
ISINK = 3 mA ISINK = 6 mA RL = 300 , CL = 35 pF, Test Circuit 5; VS1 = 3 V VS1 = 3 V, RL = 300 , CL = 35 pF; Test Circuit 5 RL = 300 , CL = 35 pF; VS1 = VS2 = 3 V, Test Circuit 5 VS = 2.5 V, RS = 0 , CL = 1 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 10 MHz; RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 8 RL = 50 , CL = 5 pF, f = 10 MHz; RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 , CL = 5 pF, Test Circuit 8
VDD = 5.5 V Digital Inputs = 0 V or 5.5 V
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SPECIFICATIONS
Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON)
1
ADG728/ADG729
(VDD = 3 V 10%, GND = 0 V, unless otherwise noted.)
B Version 25 C -40 C to +85 C 0 V to VDD 6 11 12 0.4 1.2 3.5 Unit V typ max typ max typ nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ V min V max V min V max A typ A max V min pF typ V max V max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ dB typ dB typ MHz typ MHz typ pF typ pF typ pF typ pF typ pF typ A typ A max VDD = 3.3 V Digital Inputs = 0 V or 3.3 V Test Conditions/Comments
On-Resistance Match Between Channels (RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) LOGIC INPUTS (A0, A1)2 Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Input Capacitance LOGIC INPUTS (SCL, SDA)2 Input High Voltage, VINH Input Low Voltage, VINL IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance LOGIC OUTPUT (SDA)2 VOL, Output Low Voltage DYNAMIC CHARACTERISTICS2 tON tOFF Break-Before-Make Time Delay, tD Charge Injection Off Isolation Crosstalk -3 dB Bandwidth ADG728 ADG729 CS (OFF) CD (OFF) ADG728 ADG729 CD, CS (ON) ADG728 ADG729 POWER REQUIREMENTS IDD 0.005 0.05 VDD 3 0.01 0.1 0.01 0.1 0.01 0.1
VS = 0 V to VDD, IS = 10 mA; Test Circuit 1 VS = 0 V to VDD, IS = 10 mA VS = 0 V to VDD, IS = 10 mA VDD = 3.3 V VS = 3 V/1 V, VD = 1 V/3 V, Test Circuit 2 VD = 3 V/1 V, VD = 1 V/3 V, Test Circuit 3 VD = VS = 3 V/1 V, Test Circuit 4
0.3 1 1 2.0 0.4
0.005 3
0.1
0.7 VDD VDD + 0.3 -0.3 0.3 VDD 1.0
VIN = 0 V to VDD
0.4 0.6 130 200 115 180 8 3 -55 -75 -55 -75 65 100 13 85 42 96 48 10 20 1
ISINK = 3 mA ISINK = 6 mA RL = 300 , CL = 35 pF, Test Circuit 5; VS1 = 2 V RL = 300 , CL = 35 pF; VS = 2 V, Test Circuit 5 RL = 300 , CL = 35 pF; VS1 = VS8 = 2 V, Test Circuit 5 VS = 1.5 V, RS = 0 , CL = 1 nF; Test Circuit 6 RL = 50 , CL = 5 pF, f = 10 MHz; RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 8 RL = 50 , CL = 5 pF, f = 10 MHz; RL = 50 , CL = 5 pF, f = 1 MHz; Test Circuit 7 RL = 50 , CL = 5 pF, Test Circuit 8
NOTES 1 Temperature ranges are as follows: B Versions: -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
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ADG728/ADG729
TIMING CHARACTERISTICS1 (V
Parameter fSCL t1 t2 t3 t4 t5 t6 2 t7 t8 t9 t10 t11 Limit at TMIN, TMAX 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 20 + 0.1Cb3 250 300 20 + 0.1Cb3 400 50 Unit
DD
= 2.7 V to 5.5 V. All specifications -40 C to +85 C, unless otherwise noted.)
Conditions/Comments SCL Clock Frequency SCL Cycle Time tHIGH, SCL High Time tLOW, SCL Low Time tHD, STA, Start/Repeated Start Condition Hold Time tSU, DAT, Data Setup Time tHD, DAT, Data Hold Time tSU, STA, Setup Time for Repeated Start tSU, STO, Stop Condition Setup Time tBUF, Bus Free Time Between a STOP Condition and a Start Condition tR, Rise Time of Both SCL and SDA when Receiving tF, Fall Time of SDA when Receiving tF, Fall Time of SDA when Transmitting Capacitive Load for Each Bus Line Pulsewidth of Spike Suppressed
kHz max ms min ms min ms min ms min ns min ms max ms min ms min ms min ms min ns max ns min ns max ns max ns min pF max ns max
Cb tSP4
NOTES 1 See Figure 1. 2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V IH min of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 3 Cb is the total capacitance of one bus line in pF. t R and tF measured between 0.3 V DD and 0.7 V DD. 4 Input filtering on both the SCL and SDA inputs suppress noise spikes which are less than 50 ns. Specifications subject to change without notice.
SDA
t9
t3
t 10
t 11
t4
SCL
t4
START CONDITION
t6
t2
START CONDITION
t5
t7
REPEATED START CONDITION
t1
t8
STOP CONDITION
Figure 1. 2-Wire Serial Interface Timing Diagram
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ADG728/ADG729
PIN FUNCTION DESCRIPTIONS
ADG728 1
ADG729 1
Mnemonic SCL
Function Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 8-bit input shift register. Clock rates of up to 400 kbit/s can be accommodated with this 2-wire serial interface. Active low control input that clears the input register and turns all switches to the OFF condition. Serial Data Line. This is used in conjunction with the SCL line to clock data into the 8-bit input shift register during the write cycle and used to read back 1 byte of data during the read cycle. It is a bidirectional open-drain data line which should be pulled to the supply with an external pull-up resistor. Source. May be an input or output. Drain. May be an input or output. Source. May be an input or output. Power Supply Input. These parts can be operated from a supply of 2.7 V to 5.5 V. Ground Reference. Address Input. Sets the second least significant bit of the 7-bit slave address. Address Input. Sets the least significant bit of the 7-bit slave address.
2 3 3
RESET SDA
4, 5, 6, 7 8 9, 10, 11, 12 13 14 15 16
4, 5, 6, 7 8, 9 10, 11, 12, 13 14 15 2 16
Sxx Dx Sxx VDD GND A1 A0
PIN CONFIGURATIONS ADG729
ADG728
SCL 1
RESET 2
16 A0 15 A1
SCL 1
A1 2
16 A0 15 GND
SDA 3 S1 4 S2 5 S3 6 S4 7
D8
ADG728
TOP VIEW (Not to Scale)
14 GND 13 VDD 12 S5 11 S6 10 S7 9 S8
SDA 3 S1A 4 S2A 5 S3A 6 S4A 7
DA 8
ADG729
TOP VIEW (Not to Scale)
14 VDD 13 S1B 12 S2B 11 S3B 10 S4B 9 DB
ORDERING GUIDE
Model ADG728BRU ADG729BRU
Temperature Range -40C to +85C -40C to +85C
Package Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP)
Package Option RU-16 RU-16
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ADG728/ADG729
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25C unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Analog, Digital Inputs2 . . . . . . . . . . -0.3 V to VDD + 0.3 V or 30 mA, Whichever Occurs First Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle max) Continuous Current, Each S . . . . . . . . . . . . . . . . . . . . . 30 mA Continuous Current D, ADG729 . . . . . . . . . . . . . . . . . 80 mA Continuous Current D, ADG728 . . . . . . . . . . . . . . . . 120 mA Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C
TSSOP Package JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . 27.6C/W Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300C IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S or D will be clamped by internal diodes. Current should be limited to the maximum ratings given.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG728/ADG729 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
TERMINOLOGY
VDD IDD GND S D VD (VS) RON RON RFLAT(ON)
Most Positive Power Supply Potential. Positive Supply Current. Ground (0 V) Reference. Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Analog Voltage on Terminals D, S. Ohmic Resistance between D and S. On Resistance Match Between any Two Channels, i.e., RONmax - RONmin. Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. Source Leakage Current with the Switch "OFF." Drain Leakage Current with the Switch "OFF." Channel Leakage Current with the Switch "ON." Maximum Input Voltage for Logic "0." Minimum Input Voltage for Logic "1." Input Current of the Digital Input. "OFF" Switch Source Capacitance. Measured with reference to ground. "OFF" Switch Drain Capacitance. Measured with reference to ground.
CD, CS (ON) CIN tON
"ON" Switch Capacitance. Measured with reference to ground. Digital Input Capacitance. Delay time between the 50% and 90% points of the STOP condition and the switch "ON" condition. Delay time between the 50% and 90% points of the STOP condition and the switch "OFF" condition. "OFF" time measured between the 80% points of both switches when switching from one switch to another. A measure of the glitch impulse transferred from the digital input to the analog output during switching. A measure of unwanted signal coupling through an "OFF" switch. A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. The frequency at which the output is attenuated by 3 dBs. The loss due to the ON resistance of the switch.
tOFF
tD
IS (OFF) ID (OFF) ID, IS (ON) VINL VINH IINL (IINH) CS (OFF) CD (OFF)
Charge Injection Off Isolation Crosstalk
Bandwidth
On Response The frequency response of the "ON" switch. Insertion Loss
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Typical Performance Characteristics-ADG728/ADG729
8 7 6 VDD = 2.7V TA = 25 C VSS = 0V 8 7 6 VDD = 5V VSS = 0V 8 7 6 VDD = 3V VSS = 0V
ON RESISTANCE -
ON RESISTANCE -
ON RESISTANCE -
5 4 3 2 1
VDD = 3.3V VDD = 4.5V VDD = 5.5V
5 4 3 2 1 -40 C +85 C +25 C
5 4 -40 C 3 2 1
+85 C
+25 C
0 1 2 3 4 5 0 VD OR VS - DRAIN OR SOURCE VOLTAGE - V
0 1 0 2 3 4 5 VD OR VS - DRAIN OR SOURCE VOLTAGE - V
0 0.5 1.0 1.5 2.0 2.5 3.0 0 VD OR VS - DRAIN OR SOURCE VOLTAGE - V
Figure 2. On Resistance as a Function of VD (VS) for Single Supply
Figure 3. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply
Figure 4. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply
0.12 VDD = 5V VSS = 0V TA = 25 C
0.12 VDD = 3V VSS = 0V TA = 25 C
CURRENT - nA
0.35 0.30 0.25 0.20 0.15 0.10 0.05 ID (OFF) ID (ON) VDD = 5V VSS = 0V
0.08
0.08
CURRENT - nA
CURRENT - nA
0.04
ID (ON)
0.04
ID (ON)
0.00 IS (OFF) ID (OFF)
0.00 IS (OFF)
-0.04
-0.04
ID (OFF)
-0.08
-0.08
0.00 IS (OFF) -0.05 15
-0.12
-0.12 0 1 2 3 VD (VS) - Volts 4 5
0
0.5
1.0 1.5 2.0 VD (VS) - Volts
2.5
3.0
25
35 45 55 65 TEMPERATURE - C
75
85
Figure 5. Leakage Currents as a Function of VD (VS)
Figure 6. Leakage Currents as a Function of VD (VS)
Figure 7. Leakage Currents as a Function of Temperature
0.35 0.30 0.25
CURRENT - nA
1m
VDD = 3V VSS = 0V
20 TA = 25 C 10 TA = 25 C VDD = 5V VSS = 0V
QINJ - pC
0.20 0.15 0.10 ID (OFF) 0.05 0.00 -0.05 15 IS (OFF) 25 35 45 55 65 TEMPERATURE - C ID (ON) 75 85
CURRENT - A
100 VDD = 5V
0 -10 VDD = 3V VSS = 0V
10 VDD = 3V
-20
-30
1
10k
100k FREQUENCY - Hz
1M
-40
0
1
2 3 VOLTAGE - Volts
4
5
Figure 8. Leakage Currents as a Function of Temperature
Figure 9. Input Current vs. Switching Frequency
Figure 10. Charge Injection vs. Source Voltage
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ADG728/ADG729
160 TON, VDD = 3V 140 120
TIME - ns
0 VDD = 5V TA = 25 C
0 VDD = 5V TA = 25 C
TOFF, VDD = 3V
ATTENUATION - dB
-20
-20
-40
ATTENUATION - dB
-40
100 80 TON, VDD = 5V 60 40 TOFF, VDD = 5V
-60 -80
-60 -80
-100
-100 -120 30k
20 0 -40
-120 30k 100k 1M 10M FREQUENCY - Hz 100M
100k 1M 10M FREQUENCY - Hz 100M
-20
0 20 40 60 TEMPERATURE - C
80
Figure 11. TON /TOFF Times vs. Temperature
Figure 12. Off Isolation vs. Frequency
Figure 13. Crosstalk vs. Frequency
0 VDD = 5V TA = 25 C ADG728 ADG729
ATTENUATION - dB
-5
-10
-15
-20 30k
100k
1M 10M FREQUENCY - Hz
100M
Figure 14. On Response vs. Frequency
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ADG728/ADG729
GENERAL DESCRIPTION
The ADG728 and ADG729 are serially controlled, 8-channel and dual 4-channel matrix switches respectively. While providing the normal multiplexing and demultiplexing functions, these devices also provide the user with more flexibility as to where their signal may be routed. Each bit of the serial word corresponds to one switch of the device. A Logic 1 in the particular bit position turns on the switch, while a Logic 0 turns the switch off. Because each switch is independently controlled by an individual bit, this provides the option of having any, all, or none of the switches ON. This feature may be particularly useful in the demultiplexing application where the user may wish to direct one signal from the drain to a number of outputs (sources). Care must be taken, however, in the multiplexing situation where a number of inputs may be shorted together (separated only by the small on resistance of the switch). When changing the switch conditions, a new 8-bit word is written to the input shift register. Some of the bits may be the same as the previous write cycle, as the user may not wish to change the state of some switches. In order to minimize glitches on the output of these switches, the part cleverly compares the state of switches from the previous write cycle. If the switch is already in the ON condition, and is required to stay ON, there will be minimal glitches on the output of the switch.
POWER-ON RESET
The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the Acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. However, if the R/W bit is low, the master will write to the slave device. 2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. 3. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In Write mode, the master will pull the SDA line high during the 10th clock pulse to establish a STOP condition. In Read mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse and then high during the tenth clock pulse to establish a STOP condition. See Figures 18 to 21 below for a graphical explanation of the serial interface. A repeated write function gives the user flexibility to update the matrix switch a number of times after addressing the part only once. During the write cycle, each data byte will update the configuration of the switches. For example, after the matrix switch has acknowledged its address byte, and receives one data byte, the switches will update after the data byte, if another data byte is written to the matrix switch while it is still the addressed slave device, this data byte will also cause an switch configuration update. Repeat read of the matrix switch is also allowed.
INPUT SHIFT REGISTER
On power-up of the device, all switches will be in the OFF condition and the internal shift register is filled with zeros and will remain so until a valid write takes place.
SERIAL INTERFACE 2-Wire Serial Bus
The ADG728/ADG729 are controlled via an I2C compatible serial bus. These parts are connected to this bus as a slave device (no clock is generated by the multiplexer). The ADG728/ADG729 have different 7-bit slave addresses. The five MSBs of the ADG728 are 10011, while the MSBs of the ADG729 are 10001 and the two LSBs are determined by the state of the A0 and A1 pins. The 2-wire serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address followed by a R/W bit (this bit determines whether data will be read from or written to the slave device).
The input shift register is eight bits wide. Figure 15 illustrates the contents of the input shift register. Data is loaded into the device as an 8-bit word under the control of a serial clock input, SCL. The timing diagram for this operation is shown in Figure 1. The 8-bit word consists of eight data bits each controlling one switch. MSB (Bit 7) is loaded first.
DB7 (MSB) S8 S7 S6 S5 S4 S3 DB0 (LSB) S2 S1
DATA BITS
Figure 15. ADG728/ADG729 Input Shift Register Contents
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ADG728/ADG729
WRITE OPERATION
When writing to the ADG728/ADG729, the user must begin with an address byte and R/W bit, after which the switch will acknowledge that it is prepared to receive data by pulling SDA low. This address byte is followed by the 8-bit word. The write operations for each matrix switch are shown in the figures below.
SCL
SDA START COND BY MASTER
1
0
0
1
1
A1
A0
R/W ACK BY ADG728
S8
S7
S6
S5
S4
S3
S2
S1 STOP ACK COND BY BY ADG728 MASTER
ADDRESS BYTE
DATA BYTE
Figure 16. ADG728 Write Sequence
SCL
SDA START COND BY MASTER
1
0
0
0
1
A1
A0
R/W ACK BY ADG729
S8
S7
S6
S5
S4
S3
S2
S1 STOP ACK COND BY BY ADG729 MASTER
ADDRESS BYTE
DATA BYTE
Figure 17. ADG729 Write Sequence
READ OPERATION
When reading data back from the ADG728/ADG729, the user must begin with an address byte and R/W bit, after which the matrix switch will acknowledge that it is prepared to transmit data by pulling SDA low. The readback operation is a single byte that consists of the eight data bits in the input register. The read operations for each part are shown in Figures 18 and 19.
SCL
SDA START COND BY MASTER
1
0
0
1
1
A1
A0
R/W ACK BY ADG728
S8
S7
S6
S5
S4
S3
S2
S1 NO ACK STOP COND BY BY MASTER MASTER
ADDRESS BYTE
DATA BYTE
Figure 18. ADG728 Readback Sequence
SCL
SDA START COND BY MASTER
1
0
0
0
1
A1
A0
R/W ACK BY ADG729
S8
S7
S6
S5
S4
S3
S2
S1 NO ACK STOP COND BY BY MASTER MASTER
ADDRESS BYTE
DATA BYTE
Figure 19. ADG729 Readback Sequence
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ADG728/ADG729
MULTIPLE DEVICES ON ONE BUS
Figure 20 shows four ADG728s devices on the same serial bus. Each has a different slave address since the state of their A0 and A1 pins is different. This allows each Matrix Switch to be written to or read from independently. Because the ADG729 has a different address to the ADG728, it would be possible for four of each of these devices to be connected to the same bus.
+5V RP MASTER SCL VDD SDA A1 A0 SCL SDA A1 A0 SCL VDD SDA A1 A0 SCL VDD SDA A1 A0 SCL RP SDA
ADG728
ADG728
ADG728
ADG728
Figure 20. Multiple ADG728s on the Same Bus
TEST CIRCUITS
IDS
VDD VDD S1 S2 D ID (OFF) A VD GND
V1
S
D
S8 VS
VS RON = V1/IDS
Test Circuit 1. On Resistance
VDD VDD S1 S2 VS S8 VD GND D
VS
Test Circuit 3. IS (OFF)
VDD VDD S1 S8 D
IS (OFF) A
ID (ON) A VD
GND
Test Circuit 2. ID (OFF)
Test Circuit 4. ID (ON)
VDD VDD
SCL S1 VS1
50%
50%
ADG728*
S2 THRU S7 S8 D GND VS8 RL 300 CL 35pF VOUT VS1 90% VOUT 90% VS1 = VS8 VOUT 80% 80%
tOPEN
* SIMILAR CONNECTION FOR ADG729
tOFF
tON
Test Circuit 5. Switching Times and Break-Before-Make Times
REV. 0
-11-
ADG728/ADG729
VDD VDD
ADG728*
SWITCH ON RS VS S INPUT LOGIC GND SDA SCL D CL 1nF VOUT SWITCH OFF QINJ = CL x VOUT VOUT
* SIMILAR CONNECTION FOR ADG729
Test Circuit 6. Charge Injection
VDD VDD
VDD VDD
S1 S8 VS
ADG728*
50 S1 S2 VS S8 GND D RL 50 VOUT
ADG728*
D GND VOUT
RL 50
* SIMILAR CONNECTION FOR ADG729 CHANNEL-TO-CHANNEL CROSSTALK = 20LOG10(VOUT/VS)
*SIMILAR CONNECTION FOR ADG729 S1 IS SWITCHED OFF FOR OFF ISOLATION MEASUREMENTS AND ON FOR BANDWIDTH MEASUREMENTS OFF ISOLATION = 20LOG10(VOUT/VS) INSERTION LOSS = 20LOG10 VOUT WITH SWITCH VOUT WITHOUT SWITCH
Test Circuit 7. Channel-to-Channel Crosstalk
Test Circuit 8. Off Isolation and Bandwidth
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead TSSOP (RU-16)
0.201 (5.10) 0.193 (4.90)
16
9
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 8
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
-12-
REV. 0
PRINTED IN U.S.A.
C3833-2.5-4/00 (rev. 0) 01002

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